1. Technical Field
The present invention relates to semiconductor devices including semiconductor elements whose characteristics may vary by receiving light.
2. Related Art
Semiconductor elements whose characteristics may vary by receiving light include MOS transistors, nonvolatile memories having a floating gate electrode and the like. Such semiconductor elements may receive light when mounted particularly with a COG mounting method, such as a bear chip, and as a result, in case of MOS transistors the on/off characteristics may vary, and also in case of nonvolatile memories electrons injected into the floating gate electrode may escape therefrom. In order to prevent such characteristic variations of the semiconductor elements, a light shielding layer for preventing light from being radiated is provided above regions in which such devices are provided.
JP-A-2003-124363 is an example of related art.
As one of the light shielding techniques, a technique disclosed in the example can be listed. In the related art example, there are provided an effective region of a memory cell array and a light shielding region as to enclose the outside thereof, and the light shielding region includes a via layer and a contact layer provided in different levels. Thus, this is a technique for arranging these via layer and contact layer in a staggered form to thereby suppress the intrusion of light from the lateral and diagonal directions.
However, in order to reduce the intrusion of light from the lateral and diagonal directions, even if the light shielding region is provided as to enclose the effective region of the memory cell array, there is a need or the like to extend the wirings such as signal lines to the outside of the light shielding region from the effective region of the memory cell array. For this reason, the periphery of the effective region of the memory cell array may not be enclosed completely with the via layer and the contact layer arranged in a staggered form.